Silicon IP

Silicon IP Products

Quantum Leap Solutions offers an extensive portfolio of silicon proven digital and analog IP across many process platforms. IP is available Off the Shelf or can be ported or customized to your application requirements.

  • Best in class Silicon Proven IP and ASIC solutions
  • IP customized for your application & market
  • Specifications, process offerings, and deliveries
  • Flexible IP and ASIC engagement models:
    • IP Licensing and services
    • Turnkey ASICs – specializing in wireless & mixed signal ASICs
    • Standard Product to ASIC conversion services to reduce cost & protect your IP
    • Turnkey manufacturing services for packaging, assembly and test

IP Type Offered by QLS Partners

Design IP
  • Phase Lock Loops (PLL): Integer, Low Jitter, Fractional, LC
  • SerDes 1-32G multiprotocol (PCIe gen3/4, 25GE, JESD, CPRI, etc)
  • SerDes PCS/PMA 56G, 112G (100GE, 400GE, 800GE)
  • RISC-V processors
  • eFPGA - 4K LUT tileable (Aerospace & Defense, Commercial)
  • ADC, DAC - 1MS/s to 20GS/s (radiation hardened options)
  • MIPI
  • DDR, LPDDR
  • RF and AFE subsytems
  • NOC (Custom Coherent and Non-Coherent Network on Chip)
RFIC and Wireless ASICs

IP / macro solutions for your wireless designs

  • ADC and DACs to support Lidar, Radar, 5G and SatComm applications (up to 20GS/s)
  • ADCs and DACs to support Industrial IoT, WiFi and BLE applications
  • Automotive Fusa and ASIL-B, ASIL-D design support
  • RF and mmwave macro and design expertise
  • MIMO beamforming
  • PLLs - ultra low power and low jitter options
  • RISC-V processors with DSP and Vector options
  • eFPGA fabric for protocol acceleration or encryption
  • SerDes (CPRI, JESD, 25GE, 100GE)
  • PCIe gen 3/4/5
  • RFICs and mixed signal ASICs
  • Advanced Package and Substrate design
Automotive Sensors

Automotive IP from our partners

Areas of expertise:
  • Lidar, Radar, Sensors, ADAS
  • ADC/DAC up to 20GB/s sampling (customizable)
  • ASIL-B, ASIL-D support
  • RISC-V 32 bit / 64 bit processors + DSP extensions
  • SerDes multiprotocol support
  • 25GE, Automotive Ethernet
  • MIPI C-PHY, D-PHY, A-PHY
  • PLL N3, N4, N5, N6/7, 12FFC, 16FFC
  • RFIC and Mixed Signal ASICs
  • Advanced Package / Substrate Design - automotive qualified

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Advanced Packaging Solutions

Packaging IP Partner has expertise in the following:

  • 2.5D Interposer MCM
  • RFIC package
  • Photonic IC MCM
  • Automotive MCM
  • Space-grade package
  • Biosafe Medical package
  • FlipChip BGA
  • SiP

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Chiplets

Chiplet technology is a different way of integrating multiple dies in a package or system. There are several approaches to chiplets. The basic idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme. In theory, the chiplet approach is a fast and less expensive way to assemble various types of third-party chips, such as I/Os, memory and processor cores, in a package.

With an SoC, a chip might incorporate a CPU, plus an additional 100 IP blocks on the same chip. That design is then scaled by moving to the next node, which is an expensive process. With a chiplet model, those 100 IP blocks are hardened into smaller dies or chiplets. In theory, you would have a large catalog of chiplets from various IC vendors. Then, you can mix-and-match them to build a system. Chiplets could be made at different process nodes and re-used in different designs.

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IP Partner Offerings

Andes Technologies

Andes Technology Corporation is a Taiwanese supplier of 32/64-bit embedded CPU cores and a founding Premier member of RISC-V International Association. It focuses on the embedded market and delivers CPU cores with integrated development environment and associated software and hardware for SoC development.

Andes RISC-V Solutions

1. AndeStar™ V5 Architecture: 

  • V5 is the new family of AndeStar architecture which is fully compliant with RISC-V technology while bringing extended features unique to Andes and already proven in the V3 processors, such as:
    • Andes Performance Extension to speed up common program sequence such as those for memory accesses and branches 
    •  Andes Custom Extension™ (ACE) to enable user-defined instructions for Domain-Specific Acceleration (DSA) 
    •  CoDense™ for further code size compaction 
    •  StackSafe™ stack overflow/underflow detection for program reliability 
    •  PowerBrake frequency scaling for power saving.
  • Supports both 32-bits (RV32) and 64-bits (RV64), and the latter is for applications demanding addressability greater than 4 GB or those benefiting from data wider than 32 bits.
  • Processors based on V5 architecture are supported by the same rich and easy-to-use environment as in V3 processors.   


  • 2. Facts of AndesCore™ N25F, NX25/NX25F, A25, AX25 and A27, AX27 processors:

  • Based on AndeStar™ V5 architecture:
    • 32-bit N25, N25F, D25F, A25 and A27; 64-bit NX25, NX25F, AX25, and AX27
    • N25F, NX25F, A25 and AX25 supports single and double precision floating point for high-precision data computations
    • D25F, A25 and AX25 supports DSP/SIMD instructions
    • A25/AX25 and AX27/AX27 supports MMU (Memory Management Unit) for Linux applications
  • Pipeline features:
    • Fast: Dynamic Branch Prediction, Local Memory (LM) and Caches
    • Operating above 1.1GHz with TSMC 28nm process
    • Compact: 5-stage pipeline, many features are configurable as customer's design requires
  • Support Andes Custom Extension™ (ACE) for domain-specific acceleration
  • Other key features including: ECC and parity for memory protection, configurable multiplier, well-balanced pipeline
  • Platform-Level Interrupt Controller (PLIC): To meet the common requirements of microcontrollers and real-time applications, Andes enhanced RISC-V’s PLIC with vectored interrupt dispatch, and priority-based preemption for greatly reduced interrupt service latency and easier software programming
  • Product package options: CPU subsystem pre-integrated with bus controller and AHB/AXI platforms to jump-start SoC design


  • 3. Software development environment:

  • Offer the best RISC-V compiler and most comprehensive GUI-based development environment
  • Brings the production-proven methodology for instruction customization, ACE, to RISC-V world with a complete and easy-to-use toolset and verification framework.
  • Unified development environment through the tens of thousands of installation base AndeSight IDE, to integrate supports for both mass-produced V3 processors and emerging V5 processors into one tool framework and also to ease migration works to RISC-V based ISA V5.
  • Support the popular open source FreeRTOS version 10 and also the industrial-strength ThreadX on both 32-bit and 64-bit RISC-V processors. That’s the first 64-bit RISC-V enabled ThreadX port running on AndesCore NX25.
  • Continuous contributions on RISC-V architecture port to gcc, binutils, newlib, qemu, LLVM, U-BOOT and Linux framework.


  • 4. Hardware development environment:

  • Full-featured FPGA development board
  • Compact Arduino-compatible Corvette-F1 board
  • ICE debugger


  • Ecosystem and Support

    Ecosystem:
    For the past 15 years, we have engaged over 150 partners from the fields including:

  • Hardware: connectivity, security, mixed-signal, graphics, AI …
  • Software: software stack, development tools, RTOS/middleware, voice processing…
  • Development environments for complex SoC design

  • Andes is working together with many RISC-V Foundation members to provide an advanced development environment. For example, Imperas has fast Instruction Set Simulator (ISS) and Virtual Platform that enables software development before hardware is ready; Mentor, a Siemens Business, provides Veloce Emulator that reduces risk and shortens verification of complex SoCs; UltraSoC’s embedded run control and trace IP can help debug touch bugs and identify software bottlenecks; Lauterbach’s well-known Trace32 already supported Andes N25/NX25; Andes worked with Express Logic to port the first 64-bit ThreadX RTOS to RISC-V.More and more partners are joining Andes to rich RISC-V ecosystem together.

    Support: 
    Andes supports customers with a well-established support team that have years of experiences serving its customers. 

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    eTopus is an innovator and technology leader in high performance, DSP-based, mixed-signal, ultra-high speed semiconductor interconnect solutions

    eTopus pioneered the ADC-based DSP system architecture for ultra-high speed wireline applications. The innovative architecture, which delivers superior Bit Error Rate performance for 1-112G PAM-4 SerDes IP, has been proven over multiple generations of silicon and has been adopted by Tier-1 networking, storage, and 5G OEMs. Founded in 2014, eTopus has a world-class innovation team with a track record of inventing multiple industry firsts involving mixed signal circuits with complex DSP algorithms over nearly 25 years. eTopus currently holds 10 US patents from system algorithm to circuit implementation related to the ADC/DSP-based SerDes.

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    Alphacore

    The Alphacore design team has extensive experience in delivering complete solutions for a diverse customer base, offering custom products and services that exceed performance requirements to fulfill applications needs.We can provide RF or mixed signal intellectual property (IP), specialized imaging systems, hardware-based cybersecurity solutions as well as custom design services.
    Our engineers develop innovative analog and mixed-signal components that fit niche applications and their demanding needs perfectly.

    Our focus areas are:

    • Analog, Mixed Signal and RF Solutions
    • Imaging Solutions
    • Radiation Hardened Electronics
    • Emerging Technologies


    Data Converter Architectures
    • Delta-Sigma
      • Consumer, IOT, Wearables
      • High Resolution, ultra low power
      • Lowest power up to a few MS/s
    • Pipelined
      • Consumer, WiFi, Lidar
      • High Resolution, High Dynamic Range, Moderate power
    • Hybrid SAR
      • Sat Comms, 5G, Automotive, Lidar, Exotic Compute
      • Highest Sample Rate, lowest power
    • Parallel Flash
      • Sat Comms, 5G, Automotive
      • Low Resolution, Ultra-High Speed
      • Lowest power in the industry

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    Flex Logix

    Flex Logix™ leader of embedded FPGA and AI Inferencing IP.

    Flex Logix provides eFPGA cores which have density and performance similar to leading FPGAs in the same process node but only use standard cells. Our EFLX eFPGA is silicon proven in 180nm, 40nm, 28/22nm, 16nm and 12nm with 6/7nm EFLX eFPGA is in design and 5nm next.

    Our eFPGA is based on a “tile” called EFLX 4K, which comes in two versions: all logic or mostly logic with some MACs (multiply-accumulators). The programmable logic is called LUTs (lookup tables) that can implement any Boolean function. EFLX 4K Logix has 4000 LUT4 equivalents, EFLX 4K DSP has 3000 LUT4s and 40 Multiplier-Accumulators (MACs): the MAC has a 22-bit pre-adder, a 22×22 multiple and a 48-bit post adder/accumulator. MACs can be combined or cascaded to form fast DSP functions. We can build an eFPGA array of tiles of any combination to match the requirement of the SoC (for 40nm-180nm we offer an EFLX 1K tile for smaller arrays).

    • Scalable architecture support up to 250,000 LUTs and is available on TSMC 7/12/16/22/28/40nm, GlobalFoundries 12/14nm
    • AI Inferencing IP can support 2 to 100 TOPS for more complex models

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    Mixel

    Mixel is a leading provider of mixed-signal mobile IPs. We offer a wide portfolio of high-performance mixed-signal connectivity solutions. Mixel’s mixed-signal portfolio includes PHYs and SerDes, such as MIPI® PHYs (MIPI D-PHYSM, MIPI C-PHYSM, and MIPI M-PHY®,), LVDS, and Multi-standard SerDes cores.

    Mixel’s Silicon-proven IP cores are readily available for integration into your products and are highly configurable for a wide range of applications. This allows you to develop your new systems rapidly, while dramatically reducing your risk, your time-to-market, and slashing your development and manufacturing cost.

    Our designs are robust and modular to facilitate IP core porting and customization. This enables us to meet your unique and demanding requirements in the shortest possible time with minimal risk.

    We have designed, characterized, and transferred to production our semiconductor IP cores at several leading foundries like TSMC, UMC, GlobalFoundries, SMIC, and TowerJazz, in many process technology nodes.

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    Signature IP

    Signature IP Corporation is a Silicon Valley startup, launched in 2021 after 3 years of incubation, with a focus on providing network-on-chip (NoC) IP and related SoC solutions. With rapidly growing SOC innovations in areas such as AI, 5G, and autonomous vehicles, as well as new technology such as chiplets and SIP, the dynamics of designing silicon to make it scalable, configurable and adaptable is fast changing. New designs need enhanced flexibility in their NOC IP, supporting requirements like multi-core, complex IO interactions and advanced coherency while overcoming challenges in bandwidth / latency and reducing risks of expensive silicon rework. Signature IP's vision is to enable this innovation, be adaptable, and deliver reliable SOC IP to address the ever-changing needs of the semiconductor industry.

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    Silicon Creations

    Sililcon Creations provides world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), oscillators, low-power, high-performance SerDes and high-speed differential I/Os for diverse applications including smart phones, wearables, consumer devices, processors, network devices, automotive, IoT, and medical devices. Silicon Creations' IP is proven and/or in high-volume mass production in process technologies up to the most advanced available in the industry.

    With a complete commitment to customer satisfaction, Silicon Creations’ IP has an excellent record of taking first silicon to mass production.

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