Package/Substrate Design Solutions

The QLS Sales Team

With an average of over 30 years experience in the semiconductor industry, the QLS team is a trusted advisor to companies designing SOCs and ASICs. Though all technical support is provided directly from our Partners, QLS will continue to support your project through to successful completion.

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Package/Substrate Design Solutions

Quantum Leap Solutions partner Sarcina offers Package/Substrate Design Solutions to support your IC development.

Founded in 2011, Sarcina Technology is a semiconductor packaging and testing turnkey company in Palo Alto, California, USA with a design and supply chain management office in Taipei, Taiwan. It is led by industrial veterans from places like AT&T Bell Labs, DEC, Intel and TSMC.

Sarcina Technology provides leading US companies with package design and power/signal integrity simulation. In addition, Sarcina offers wafer probing and final test hardware design, test program development, and one-stop turnkey service.

We work with the world's foremost foundries to ensure high quality products. We've handled everything, from the simplest to the most complex of packages. Our results are self-evident: since its formation, Sarcina's tapeouts have all been first-time successes.

In 2018, Sarcina expanded its package assembly and final test service. Today, our business model is wafer-in, chip-out. Customers send us their bumped wafers from foundries and we design the final test hardware and convert DFT test patterns to ATE test vectors. Sarcina handles all the logistics.

Sarcina Tech
  • Founded in 2011 in Palo Alto, CA
  • Providing uncompromised semiconductory Turnkey Services:
    • Package substrate Design & Fabrication, Assembly & Test, Qulification, Production
  • Experts in Advanced Package design (MCM, RF, Automotive, uProcessor)
  • Turnkey manufacturing from fabricated wafers to chips
    • Wafers-in to Chips-out
    • Prototype and Production services
  • Technologies
    • Package Design
    • Model Extraction
    • Simulation
    • Channel Simulation
    • Design for Manufacturing
    • SiP and MCM
    • 56 Gb/s PAM-4
    • Wafer Probe Card
    • Final Test Hardware
    • Test Program Developmet
  • Locations: Silicon Valley, USA; Taipei, Taiwan

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