Andes Technology Corporation is a Taiwanese supplier of 32/64-bit embedded CPU cores and a founding Premier member of RISC-V International Association. It focuses on the embedded market and delivers CPU cores with integrated development environment and associated software and hardware for SoC development.
V5 is the new family of AndeStar architecture which is fully compliant with RISC-V technology while bringing extended features unique to Andes and already proven in the V3 processors, such as:
Andes RISC-V Solutions
1. AndeStar™ V5 Architecture:
Supports both 32-bits (RV32) and 64-bits (RV64), and the latter is for applications demanding addressability greater than 4 GB or those benefiting from data wider than 32 bits.
Processors based on V5 architecture are supported by the same rich and easy-to-use environment as in V3 processors.
- Andes Performance Extension to speed up common program sequence such as those for memory accesses and branches
- Andes Custom Extension™ (ACE) to enable user-defined instructions for Domain-Specific Acceleration (DSA)
- CoDense™ for further code size compaction
- StackSafe™ stack overflow/underflow detection for program reliability
- PowerBrake frequency scaling for power saving.
2. Facts of AndesCore™ N25F, NX25/NX25F, A25, AX25 and A27, AX27 processors:
Based on AndeStar™ V5 architecture:
- 32-bit N25, N25F, D25F, A25 and A27; 64-bit NX25, NX25F, AX25, and AX27
- N25F, NX25F, A25 and AX25 supports single and double precision floating point for high-precision data computations
- D25F, A25 and AX25 supports DSP/SIMD instructions
- A25/AX25 and AX27/AX27 supports MMU (Memory Management Unit) for Linux applications
Support Andes Custom Extension™ (ACE) for domain-specific acceleration
Other key features including: ECC and parity for memory protection, configurable multiplier, well-balanced pipeline
Platform-Level Interrupt Controller (PLIC): To meet the common requirements of microcontrollers and real-time applications, Andes enhanced RISC-V’s PLIC with vectored interrupt dispatch, and priority-based preemption for greatly reduced interrupt service latency and easier software programming
Product package options: CPU subsystem pre-integrated with bus controller and AHB/AXI platforms to jump-start SoC design
- Fast: Dynamic Branch Prediction, Local Memory (LM) and Caches
- Operating above 1.1GHz with TSMC 28nm process
- Compact: 5-stage pipeline, many features are configurable as customer's design requires
3. Software development environment:
Offer the best RISC-V compiler and most comprehensive GUI-based development environment
Brings the production-proven methodology for instruction customization, ACE, to RISC-V world with a complete and easy-to-use toolset and verification framework.
Unified development environment through the tens of thousands of installation base AndeSight IDE, to integrate supports for both mass-produced V3 processors and emerging V5 processors into one tool framework and also to ease migration works to RISC-V based ISA V5.
Support the popular open source FreeRTOS version 10 and also the industrial-strength ThreadX on both 32-bit and 64-bit RISC-V processors. That’s the first 64-bit RISC-V enabled ThreadX port running on AndesCore NX25.
Continuous contributions on RISC-V architecture port to gcc, binutils, newlib, qemu, LLVM, U-BOOT and Linux framework.
4. Hardware development environment:
Full-featured FPGA development board
Compact Arduino-compatible Corvette-F1 board
Ecosystem and Support
Hardware: connectivity, security, mixed-signal, graphics, AI …
Software: software stack, development tools, RTOS/middleware, voice processing…
Development environments for complex SoC design
For the past 15 years, we have engaged over 150 partners from the fields including:
Andes is working together with many RISC-V Foundation members to provide an advanced development environment. For example, Imperas has fast Instruction Set Simulator (ISS) and Virtual Platform that enables software development before hardware is ready; Mentor, a Siemens Business, provides Veloce Emulator that reduces risk and shortens verification of complex SoCs; UltraSoC’s embedded run control and trace IP can help debug touch bugs and identify software bottlenecks; Lauterbach’s well-known Trace32 already supported Andes N25/NX25; Andes worked with Express Logic to port the first 64-bit ThreadX RTOS to RISC-V.More and more partners are joining Andes to rich RISC-V ecosystem together.
Andes supports customers with a well-established support team that have years of experiences serving its customers.
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